A NAND gate is called a universal logic element because______________?

Related Mcqs:

A debouncing circuit is________________?

A. an astable MV B. a bistable MV C. a latch D. a monostable MV...

Positive logic in a logic circuit is one in which______________?

A. logic 0 and 1 are represented by 0 and positive voltage respectively B. logic 0 and, -1 are represented by negative and positive voltages respectively C. logic 0 voltage level is higher than logic 1 voltage level D. logic 0 voltage level is lower than logic 1 voltage level...

Which is the correct order of sequence for representing the input values in K-map ?

A. (00, 01, 10, 11) B. (00, 10, 01, 11) C. (00, 01, 11, 10) D. (00, 10, 11, 01)...

The NOR gate is OR gate followed by____________________?

A. AND gate B. NAND gate C. NOT gate D. None of the above...

The inputs of a NAND gate are connected together. The resulting circuit is _______________?

A. OR gate B. AND gate C. NOT gate D. None of the above...